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preliminary rev. 0.6 7/15 copyright ? 2015 by silicon laboratories si88x4x this information applies to a product under development. its characteristics and specifications are subject to change without n otice. si88x4x q uad d igital i solators with dc-dc c onverter features applications safety approval (pending) description the si88xx integrates silicon labs? prov en digital isolator technology with an on-chip isolated dc-dc converter that provides regulated output voltages of 3.3 or 5.0 v (or >5 v with external components) at peak output power levels of up to 5 w. these devices provide up to four digital channels. the dc-dc converter has user-adjustable frequency for minimizing emissions, a soft-start function for safety, a shut-down option and loop compensation. the device requires only minimal passive components and a miniature transformer. the ultra-low-power digital isolation channels offer substantial data rate, propagation delay, size and reliability advantages over legacy isolation technologies. data rates up to 100 mbps max are supported, and all devices achieve propagation delays of only 23 ns max. ordering options include a choice of dc-dc converter features, isolation channel configurations and a fail- safe mode. all products are certified by ul, csa, vde, and cqc. ? high-speed isolators with integrated dc-dc converter ? fully-integrated secondary sensing feedback-controlled converter with dithering for low emi ? dc-dc converter peak efficiency of 83% with external power switch ? up to 5 w isolated power with external power switch ? options include dc-dc shutdown, frequency control, and soft start ? standard voltage conversion ?? 3/5 v to isolated 3/5 v ?? 24 v to isolated 3/5 v supported ? precise timing on digital isolators ?? 0?100 mbps ?? 18 ns typical prop delay ? highly-reliable: 100 year lifetime ? high electromagnetic immunity and ultra-low emissions ? rohs compliant packages ?? soic-20 wide body ?? soic-24 wide body ? isolation of up to 5000 vrms ? high transient immunity of 100 kv/s (typical) ? aec-q100 qualified ? wide temp range ?? ?40 to +125 c ? industrial automation systems ? hybrid electric and electric vehicles ? isolated power supplies ? inverters ? data acquisition ? motor control ? plcs, distributed control systems ? ul 1577 recognized ?? up to 5000 vrms for 1 minute ?? csa component notice 5a approval ? vde certification conformity ?? vde 0884-10 ? cqc certification approval ?? gb4943.1 patents pending ordering information: see page 38. pin assignments see page 33 isolation ? barrier 1 2 3 4 5 6 9 10 20 19 18 17 16 15 12 11 hf xmtr hf xmtr hf rcvr hf rcvr gndp vsw vddp vdda gnda sh a3 a4 gndb vddb dnc nc vsns comp b3 b4 7 8 14 13 a1 a2 b1 b2 hf xmtr hf xmtr hf rcvr hf rcvr si88240
si88x4x 2 preliminary rev. 0.6 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 2.1. theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2. digital isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 2.3. dc-dc converter applicat ion information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.4. transformer design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3. digital isolator device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1. device startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.2. undervoltage lo ckout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3. layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4. fail-safe operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.5. typical performance char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6. package outline: 20-pin wide body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7. land pattern: 20-pin soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1 8. package outline: 24-pin wide body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9. land pattern: 24-pin soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 4 10. top markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.1. si88x4x top marking (20-pin wide body soic) . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.2. top marking explanati on (20-pin wide body soic ) . . . . . . . . . . . . . . . . . . . . . . . 45 10.3. si88x4x top marking (24-pin wide body soic) . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.4. top marking explanati on (24-pin wide body soic ) . . . . . . . . . . . . . . . . . . . . . . . 46 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 contact inform ation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
si88x4x preliminary rev. 0.6 3 1. electrical specifications table 1. recommended operating conditions parameter symbol min typ max unit ambient operating temperature* t a ? 4 02 51 2 5 c power input voltage vddp 3.0 ? 5.5 v supply voltage vdda 3.0 ? 5.5 v vddb 3.0 ? 5.5 v *note: the maximum ambient temperature is dependent on data fr equency, output loading, num ber of operating channels, and supply voltage. table 2. electrical characteristics 1 v in =24v; v dda = 4.3 v (see figure 3) for all si8844x/64x; v dda =v ddp = 3.0 to 5.5 v (see figure 2) for all si8824x/34x; t a = ?40 to 125 c unless otherwise noted parameter symbol test condition min typ max unit dc/dc converter switching frequency si8824x, si8844x fsw 250 khz switching frequency si8834x, si8864x fsw rfsw = 23.3 k ? fsw = 1025.5/(rfsw x css) css = 220 nf (see figure 9) (1% tolerance on bom) 180 200 220 khz rfsw = 9.3 k ? fsw = 1025.5/(rfsw x css) css = 220 nf (see figure 9) (1% tolerance on bom) 450 500 550 khz rfsw = 5.18 k ? , css = 220 nf (see figure 9) 810 900 990 khz vsns voltage vsns iload = 0 a 1.002 1.05 1.097 v vsns current offset i offset ?500 ? 500 na notes: 1. over recommended operating conditions as noted in table 1. 2. vout = vsns x (1 + r1/r2) + r1 x i offset 3. vddp current needed for dc-dc circuits. 4. vdda current needed for dc-dc circuits. 5. the nominal output impedance of an isolator driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driv er fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 6. tpsk(p-p) is the magnitude of the differ ence in propagation delay times measur ed between different units operating at the same supply voltages, lo ad, and ambient temperature. 7. start-up time is the time period from when the uvlo threshold is exceeded to valid data at the output.
si88x4x 4 preliminary rev. 0.6 output voltage accuracy 2 see figure 2 iload = 0 ma ?5 ? +5 % line regulation ? vout(line)/ ? v ddp see figure 2 iload = 50 ma vddp varies from 4.5 to 5.5 v 1mv/v load regulation ? vout(load)/v out see figure 2 iload = 50 to 400 ma 0.1 % output voltage ripple si8824x, si8834x si8844x, si8864x iload = 100 ma see figure 2 see figure 3 100 mv p-p turn-on overshoot ? vout(start) see figure 2 cin = cout = 0.1 f in parallel with 10 f, iload = 0 a 2% continuous ou tput current si8824x, si8834x 5.0 v to 5.0 v 3.3 v to 3.3 v 3.3 v to 5.0 v 5.0 v to 3.3 v si8844x, si8864x 24.0 to 5.0 v 24.0 to 3.0 v iload(max) see figure 2 see figure 3 400 400 250 550 1000 1500 ma cycle-by-cycle average current limit si8824x, si8834x ilim see figure 2 output short circuited 3a no load supply current iddp si8824x, si8834x iddpq_dcdc 3 see figure 2 vddp = vdda = 5 v 30 ma no load supply current idda si8824x, si8834x iddaq_dcdc 4 see figure 2 vddp = vdda = 5 v 5.7 ma table 2. electrical characteristics 1 (continued) v in =24v; v dda = 4.3 v (see figure 3) for all si8844x/64x; v dda =v ddp = 3.0 to 5.5 v (see figure 2) for all si8824x/34x; t a = ?40 to 125 c unless otherwise noted parameter symbol test condition min typ max unit notes: 1. over recommended operating conditions as noted in table 1. 2. vout = vsns x (1 + r1/r2) + r1 x i offset 3. vddp current needed for dc-dc circuits. 4. vdda current needed for dc-dc circuits. 5. the nominal output impedance of an isolator driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driv er fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 6. tpsk(p-p) is the magnitude of the differ ence in propagation delay times measur ed between different units operating at the same supply voltages, lo ad, and ambient temperature. 7. start-up time is the time period from when the uvlo threshold is exceeded to valid data at the output.
si88x4x preliminary rev. 0.6 5 no load supply current iddp si8844x, si8864x iddpq_dcdc 3 see figure 3 vin = 24 v 0.8 ma no load supply current idda si8844x, si8864x iddaq_dcdc 4 see figure 3 vin = 24 v 5.8 ma peak efficiency si8824x, si8834x si8844x, si8864x ? see figure 2, 3 78 83 % voltage regulator refer- ence voltage si8844x, si8864x vrega, vregb i reg =600a see figure 30 for typical i?v curve 4.8 v vreg tempco k tvreg ?0.43 mv/c vreg input current i reg 350 ? 950 a soft start time, full load si8824x, si8844x si8834x, si8864x t sst see figures 25 through 28 for typical soft start times over load conditions. 25 50 ms restart delay from fault event totp 21 s digital isolator vdd undervoltage threshold vdduv+ vdda, vddb rising 2.7 v vdd undervoltage threshold vdduv? vdda, vddb falling 2.6 v vdd undervoltage hysteresis vdd hys 100 mv positive-going input threshold vt+ all inputs rising 1.67 v table 2. electrical characteristics 1 (continued) v in =24v; v dda = 4.3 v (see figure 3) for all si8844x/64x; v dda =v ddp = 3.0 to 5.5 v (see figure 2) for all si8824x/34x; t a = ?40 to 125 c unless otherwise noted parameter symbol test condition min typ max unit notes: 1. over recommended operating conditions as noted in table 1. 2. vout = vsns x (1 + r1/r2) + r1 x i offset 3. vddp current needed for dc-dc circuits. 4. vdda current needed for dc-dc circuits. 5. the nominal output impedance of an isolator driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driv er fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 6. tpsk(p-p) is the magnitude of the differ ence in propagation delay times measur ed between different units operating at the same supply voltages, lo ad, and ambient temperature. 7. start-up time is the time period from when the uvlo threshold is exceeded to valid data at the output.
si88x4x 6 preliminary rev. 0.6 negative-going input threshold vt? all inputs falling 1.23 v input hysteresis v hys 0.44 v high level input voltage v ih 2.0 ? ? v low level input voltage v il ??0.8 v high level output voltage v oh loh = ?4 ma v dda , v ddb ? 0.4 ?? v low level output voltage v ol lol = 4 ma ? ? 0.4 v input leakage current i l ??10a output impedance z o ?50? ? supply current, c load =15pf dc, vddx = 3.3 v 10% si88x40 v dda v ddb v dda v ddb all inputs = 0 all inputs = 0 all inputs = 1 all inputs = 1 ? ? ? ? 12.9 5.4 5.1 5.3 ma si88x41 v dda v ddb v dda v ddb all inputs = 0 all inputs = 0 all inputs = 1 all inputs = 1 ? ? ? ? 10.9 6.8 5.6 5.1 ma si88x42 v dda v ddb v dda v ddb all inputs = 0 all inputs = 0 all inputs = 1 all inputs = 1 ? ? ? ? 9.7 7.8 5.9 4.3 ma table 2. electrical characteristics 1 (continued) v in =24v; v dda = 4.3 v (see figure 3) for all si8844x/64x; v dda =v ddp = 3.0 to 5.5 v (see figure 2) for all si8824x/34x; t a = ?40 to 125 c unless otherwise noted parameter symbol test condition min typ max unit notes: 1. over recommended operating conditions as noted in table 1. 2. vout = vsns x (1 + r1/r2) + r1 x i offset 3. vddp current needed for dc-dc circuits. 4. vdda current needed for dc-dc circuits. 5. the nominal output impedance of an isolator driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driv er fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 6. tpsk(p-p) is the magnitude of the differ ence in propagation delay times measur ed between different units operating at the same supply voltages, lo ad, and ambient temperature. 7. start-up time is the time period from when the uvlo threshold is exceeded to valid data at the output.
si88x4x preliminary rev. 0.6 7 si88x43 v dda v ddb v dda v ddb all inputs = 0 all inputs = 0 all inputs = 1 all inputs = 1 ? ? ? ? 8.5 9.3 6.5 3.9 ma si88x44 v dda v ddb v dda v ddb all inputs = 0 all inputs = 0 all inputs = 1 all inputs = 1 ? ? ? ? 6.6 10.6 6.5 3.6 ma 1 mbps, vddx = 3.3 v 10% (all inputs = 500 khz square wave, c load =15pf) si88x40 v dda v ddb ? ? 8.9 5.4 ma si88x41 v dda v ddb ? ? 8.3 6.0 ma si88x42 v dda v ddb ? ? 7.9 6.1 ma si88x43 v dda v ddb ? ? 7.6 6.7 ma si88x44 v dda v ddb ? ? 6.7 7.1 ma 100 mbps, vddx = 3.3 v 10% (all inputs = 50 mhz square wave, c load = 15 pf) si88x40 v dda v ddb ? ? 8.7 19.2 ma table 2. electrical characteristics 1 (continued) v in =24v; v dda = 4.3 v (see figure 3) for all si8844x/64x; v dda =v ddp = 3.0 to 5.5 v (see figure 2) for all si8824x/34x; t a = ?40 to 125 c unless otherwise noted parameter symbol test condition min typ max unit notes: 1. over recommended operating conditions as noted in table 1. 2. vout = vsns x (1 + r1/r2) + r1 x i offset 3. vddp current needed for dc-dc circuits. 4. vdda current needed for dc-dc circuits. 5. the nominal output impedance of an isolator driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driv er fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 6. tpsk(p-p) is the magnitude of the differ ence in propagation delay times measur ed between different units operating at the same supply voltages, lo ad, and ambient temperature. 7. start-up time is the time period from when the uvlo threshold is exceeded to valid data at the output.
si88x4x 8 preliminary rev. 0.6 si88x41 v dda v ddb ? ? 12.7 16.6 ma si88x42 v dda v ddb ? ? 15.6 13.6 ma si88x43 v dda v ddb ? ? 18.7 11.0 ma si88x44 v dda v ddb ? ? 21.6 6.9 ma table 2. electrical characteristics 1 (continued) v in =24v; v dda = 4.3 v (see figure 3) for all si8844x/64x; v dda =v ddp = 3.0 to 5.5 v (see figure 2) for all si8824x/34x; t a = ?40 to 125 c unless otherwise noted parameter symbol test condition min typ max unit notes: 1. over recommended operating conditions as noted in table 1. 2. vout = vsns x (1 + r1/r2) + r1 x i offset 3. vddp current needed for dc-dc circuits. 4. vdda current needed for dc-dc circuits. 5. the nominal output impedance of an isolator driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driv er fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 6. tpsk(p-p) is the magnitude of the differ ence in propagation delay times measur ed between different units operating at the same supply voltages, lo ad, and ambient temperature. 7. start-up time is the time period from when the uvlo threshold is exceeded to valid data at the output.
si88x4x preliminary rev. 0.6 9 dc, vddx = 5 v 10% si88x40 v dda v ddb v dda v ddb all inputs = 0 all inputs = 0 all inputs = 1 all inputs = 1 ? ? ? ? 13.1 5.6 5.2 5.4 ma si88x41 v dda v ddb v dda v ddb all inputs = 0 all inputs = 0 all inputs = 1 all inputs = 1 ? ? ? ? 11.1 6.9 5.7 5.2 ma si88x42 v dda v ddb v dda v ddb all inputs = 0 all inputs = 0 all inputs = 1 all inputs = 1 ? ? ? ? 10.1 7.9 6.2 4.4 ma si88x43 v dda v ddb v dda v ddb all inputs = 0 all inputs = 0 all inputs = 1 all inputs = 1 ? ? ? ? 8.6 9.2 6.6 3.9 ma si88x44 v dda v ddb v dda v ddb all inputs = 0 all inputs = 0 all inputs = 1 all inputs = 1 ? ? ? ? 6.8 11.0 6.7 3.8 ma 1 mbps, vddx = 5 v 10% (all inputs = 500 khz square wave, c load =15pf) si88x40 v dda v ddb ? ? 9.1 5.8 ma table 2. electrical characteristics 1 (continued) v in =24v; v dda = 4.3 v (see figure 3) for all si8844x/64x; v dda =v ddp = 3.0 to 5.5 v (see figure 2) for all si8824x/34x; t a = ?40 to 125 c unless otherwise noted parameter symbol test condition min typ max unit notes: 1. over recommended operating conditions as noted in table 1. 2. vout = vsns x (1 + r1/r2) + r1 x i offset 3. vddp current needed for dc-dc circuits. 4. vdda current needed for dc-dc circuits. 5. the nominal output impedance of an isolator driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driv er fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 6. tpsk(p-p) is the magnitude of the differ ence in propagation delay times measur ed between different units operating at the same supply voltages, lo ad, and ambient temperature. 7. start-up time is the time period from when the uvlo threshold is exceeded to valid data at the output.
si88x4x 10 preliminary rev. 0.6 si88x41 v dda v ddb ? ? 8.4 6.3 ma si88x42 v dda v ddb ? ? 8.2 6.2 ma si88x43 v dda v ddb ? ? 7.8 6.7 ma si88x44 v dda v ddb ? ? 6.9 7.4 ma 100 mbps, vddx = 5 v 10% (all inputs = 50 mhz square wave, c load = 15 pf) si88x40 v dda v ddb ? ? 8.2 26.2 ma si88x41 v dda v ddb ? ? 14.7 22.0 ma si88x42 v dda v ddb ? ? 18.9 16.5 ma si88x43 v dda v ddb ? ? 24.0 11.7 ma si88x44 v dda v ddb 28.1 6.6 ma timing characteristics data rate 0 ? 100 mbps table 2. electrical characteristics 1 (continued) v in =24v; v dda = 4.3 v (see figure 3) for all si8844x/64x; v dda =v ddp = 3.0 to 5.5 v (see figure 2) for all si8824x/34x; t a = ?40 to 125 c unless otherwise noted parameter symbol test condition min typ max unit notes: 1. over recommended operating conditions as noted in table 1. 2. vout = vsns x (1 + r1/r2) + r1 x i offset 3. vddp current needed for dc-dc circuits. 4. vdda current needed for dc-dc circuits. 5. the nominal output impedance of an isolator driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driv er fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 6. tpsk(p-p) is the magnitude of the differ ence in propagation delay times measur ed between different units operating at the same supply voltages, lo ad, and ambient temperature. 7. start-up time is the time period from when the uvlo threshold is exceeded to valid data at the output.
si88x4x preliminary rev. 0.6 11 minimum pulse width 10 ? ? ns propagation delay t phl see figure 1 vddx = 3.3 v ? 17.8 ? ns propagation delay t plh see figure 1 vddx = 3.3 v ? 14.5 ? ns propagation delay t phl see figure 1 vddx = 5.0 v ? 17.5 ? ns propagation delay t plh see figure 1 vddx = 5.0 v ? 12.6 ? ns pulse width distortion |t plh ? t phl | pwd see figure 1 vddx = 3.3 v ?3.4? ns pulse width distortion |t plh ? t phl | pwd see figure 1 vddx = 5.0 v ?4.8? ns propagation delay skew 6 t psk(p-p) ?2.0? ns channel-channel skew t psk ?1.0? ns output rise time t r c load = 15 pf ? 2.5 ? ns output fall time t f c load = 15 pf ? 2.5 ? ns common mode transient immunity cmti v i =vddx or 0v v cm =1500v see figure 4 40 100 ? kv/s startup time 7 t su ?55? s table 2. electrical characteristics 1 (continued) v in =24v; v dda = 4.3 v (see figure 3) for all si8844x/64x; v dda =v ddp = 3.0 to 5.5 v (see figure 2) for all si8824x/34x; t a = ?40 to 125 c unless otherwise noted parameter symbol test condition min typ max unit notes: 1. over recommended operating conditions as noted in table 1. 2. vout = vsns x (1 + r1/r2) + r1 x i offset 3. vddp current needed for dc-dc circuits. 4. vdda current needed for dc-dc circuits. 5. the nominal output impedance of an isolator driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driv er fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 6. tpsk(p-p) is the magnitude of the differ ence in propagation delay times measur ed between different units operating at the same supply voltages, lo ad, and ambient temperature. 7. start-up time is the time period from when the uvlo threshold is exceeded to valid data at the output.
si88x4x 12 preliminary rev. 0.6 figure 1. propagation delay timing for digital channels figure 2. measurement circuit for converter efficiency and regulation for si882xx, si883xx typical input t plh t phl typical output t r t f 90% 10% 90% 10% 1.4 v 1.4 v v in i in c2 10 f 10 f c1 t1 d1 db2440100l r4 100 c5 100 pf utb02185s i ddb u1 i ddp i dda vsw vddp vdda sh gnda gndp gndb comp vsns vddb isolation r3 49.9 k c4 1.5 nf r2 13.3 k r1 49.9 k c3 10 f v out + _ + _
si88x4x preliminary rev. 0.6 13 figure 3. measurement circuit for converter efficiency and regulation for si884xx, si886xx figure 4. common-mode transient immunity test circuit i load i ddp i in v in + _ c2 10 f i dda isolation v out + _ c3 22 f sbrt5a50sa r8 27.4 c6 100 pf utb02205s d1 t1 q1 i ddb fdt3612 r7 19.6 k q2 mmbt2222lt1 r5 0.1 u2 r1 49.9 k r2 13.3 k r3 100 k c4 1.5 nf c5 0.1 f r6 18 k c1 0.22 f gnda sh_fc ss vdda vreg gndp rsns esw vddb vsns comp gndb r9 82 c7 68 pf c8 10 f + _ si8824x vsw vddp/vdda vddb gnda gndb high voltage transient generator reverse channel output forward channel input forward channel ouput reverse channel input isolated supply dc-dc output powers b-side referenced to earth ground reverse channel measured by forward channel in loopback high voltage differential probe oscilloscope
si88x4x 14 preliminary rev. 0.6 table 3. regulatory information 1,2 csa the si88xx is certified under csa component accept ance notice 5a. for more details, see file 232873. vde the si88xx is certified according to vde 0884-10. for more details, see file 5006301-4880-0001. vde 0884-10: up to 891 v peak for basic insulation working voltage. ul the si88xx is certified under ul1577 component recognition program. for more details, see file e257455. rated up to 5000 v rms isolation voltage for basic protection. cqc the si88xx is certified under gb4943.1-2011. rated up to 600 v rms reinforced insulation working voltage; up to 1000 v rms basic insulation working voltage. notes: 1. regulatory certifications apply to 5 kvrms rated devic es which are production tested to 6.0 kvrms for 1 sec. 2. all certifications are pending.
si88x4x preliminary rev. 0.6 15 table 4. insulation and safety-related specifications parameter symbol test condition value unit wb soic-20 wb soic-24 nominal air gap (clearance) l(1o1) 8.0 1 mm nominal external tracking (creepage) l(1o2) 8.0 1 mm minimum internal gap (internal clearance) 0.014 mm tracking resistance (proof tracking index) pti iec60112 600 v erosion depth ed 0.019 mm resistance (input-output) 2 r io 10 12 ? capacitance (input-output) 2 c io f=1mhz 1.4 pf input capacitance 3 c i 4.0 pf notes: 1. the values in this table correspond to the nominal creep age and clearance values. vde certifies the clearance and creepage limits as 8.5 mm minimum for the wb soic-20 and wb soic-24 packages. ul does not impose a clearance and creepage minimum for component-level certifications. csa certifies the clearance and creepage limits as 7.6 mm minimum for the wb soic-20 and wb soic-24 packages. 2. to determine resistance and capacitance, the si88xx is converted into a 2-terminal device. pins 1?8 are shorted together to form the first terminal and pi ns 9?16 are shorted together to form th e second terminal. the parameters are then measured between these two terminals. 3. measured from input to ground. table 5. iec 60664-1 (vde 0884-10) ratings parameter test cond ition specification wb soic-20 wb soic-24 basic isolation group material group i installation classification rate mains voltages < 150 v rms i?iv rate mains voltages < 300 v rms i?iv rate mains voltages < 400 v rms i?iii rate mains voltages < 600 v rms i?iii
si88x4x 16 preliminary rev. 0.6 table 6. vde 0884-10 insulation characteristics* parameter symbol test condition characteristic unit wb soic-20 wb soic-24 maximum working insulation voltage v iorm 891 v peak input to output test voltage v pr method b1 (v iorm x1.875=v pr , 100% production test, t m = 1 sec, partial discharge < 5 pc) 1671 v peak transient overvoltage v iotm t = 60 sec 6000 v peak pollution degree (din vde 0110, table 1) 2 insulation resistance at t s , v io =500v r s >10 9 ? *note: maintenance of the safety data is ensu red by protective circuits. the si88xx provides a climate classification of 40/125/21. table 7. iec safety limiting values* parameter symbol test condition wb soic-20 unit case temperature t s 150 c safety input current i s ? ja = 55 c/w (wb soic-20), v dda =5.5v, t j =150c, t a =25c 413 ma device power dissipation p d 2.27 w *note: maximum value allowed in the event of a failure. refer to the thermal derating curve in figure 3.
si88x4x preliminary rev. 0.6 17 figure 5. wb soic-20 thermal derating curve* *note: values are not final and are subject to change. dependence of safety limiting values with case temperature per vde 0884-10. table 8. thermal characteristics parameter symbol wb soic-20 unit ic junction-to-air thermal resistance ? ja 55 c/w 631 413 0 100 200 300 400 500 600 700 0 20 40 60 80 100 120 140 160 safety limit current, ma temperature o c 3.6v 5.5v
si88x4x 18 preliminary rev. 0.6 table 9. absolute maximum ratings 1,2 parameter symbol min max unit storage temperature t stg ?65 +150 c junction temperature t j ?+150 c input-side supply voltage vdda vddp ?0.6 6.0 v output supply vddb ?0.6 6.0 v voltage on any pin with respec t to ground vin ?0.5 vdd + 0.5 v output drive current per channel i o 10 ma input current for vrega, vregb i reg ?1m a lead solder temperature (10 s) ? 260 c esd per aec-q100 hbm ? 4 kv cdm ? 2 kv maximum isolation (input to output) (1 sec) wb soic-20, wb soic-24 ? 6500 v rms notes: 1. permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. vde certifies storage temperature from ?40 to 150 c.
si88x4x preliminary rev. 0.6 19 2. functional description 2.1. theory of operation the si88xx family of products is capable of transmitting and receiving digital data signals from an isolated power domain to a local system power domain with up to 5 kv of isolation. each part has four unidirectional digital isolation channels. in addition, si88xx products include an integrated controller and switches for a dc-dc converter which regulates output voltage by sensing it on the isolated side. 2.2. digital isolation the operation of an si88xx digital chan nel is analogous to that of a digital buffer, except an rf carrier transmits data across the isolation barrier. this simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. a simplified block diagram for a single si88xx channel is shown in figure 6. figure 6. simplified si88xx channel diagram a channel consists of an rf transmitter and rf receiv er separated by a silicon di oxide capacitive isolation barrier. in the transmitter, input a modulates the carrie r provided by an rf oscilla tor using on/off keying. the receiver contains a demodulator that decodes the input st ate according to its rf energy content and applies the result to output b via the output driver. this rf on/o ff keying scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. see figure 7 for more details. figure 7. modulation scheme rf oscillator modulator demodulator a b semiconductor- based isolation barrier transmitter receiver input signal output signal modulation signal
si88x4x 20 preliminary rev. 0.6 2.3. dc-dc converter application information the si88xx isolated dc-dc converter is based on a modified fly-back topology and uses an external transformer and schottky rectifying diode for low cost and high operat ing efficiency. the pwm controller operates in closed-loop, peak current mode control and generates isolated output voltages with 2 w average out put power at 5.0 v. options are available for 24 vdc input or output operation and externally configured switching frequency. the dc-dc controller modulates a pair of internal primary-side power switches (see figure 8) to generate an isolated voltage at external diode d1 cathode. closed-loop feedback is provided by a compensated error amplifier, which compares the voltage at the vsns pin to an internal voltage reference. the resulting error voltage is fed back through the isolation barrier via an internal feedback path to the controller, thus completing the control loop. for higher input supply voltages than 5 v, an external fe t q2 is modulated by a driver pin esw as shown in (see figure 9). a shunt resistor based voltage sens e pin rsn provides current sens ing capability to the controller. additional features include an externally-triggered shutdow n of the converter functionality using the sh pin and a programmable soft start configured by a capacitor connected to the ss pin. the si88xx can be used in low- or high- voltage configurations. these features and conf igurations are explained in more detail below. 2.3.1. shutdown this feature allows the operation of the dc-dc converter to be shut down when asserted high. this function is provided by pin 6 (labeled ?sh? on the si882xx) and pin 7 (labeled ?sh_fc? on the si883xx and si886xx). this feature is not available on the si884xx. pin 6 or pin 7 provide the exact same functionality and shut down the dc-dc converter when asserted high. for normal operation, pins 6 and 7 should be connected to ground. 2.3.2. soft-start the dc-dc controller has an internal timer that controls the power conversion start-up to limit inrush current. there is also the soft start option where users can program the soft start up by an external capacitor connected to the ss pin. this feature is available on the si883xx and the si886xx. 2.3.3. programmable frequency the frequency of the pwm modulator is set to a defaul t of 250 khz for si882xx/4x x. users can program their desired frequency within a given band of 200 khz to 800 khz by controllin g the time constant of an external rc connected to the sh_fc and ss pins for si883xx/6xx. 2.3.4. external transformer driver the dc-dc controller has internal switch es (vsw) for driving the transformer with up-to a 5.5 v voltage supply. for higher voltages on the primary side, a driver output (esw ) is provided that can drive an external nmos power transistor for driving the transformer. when this configur ation is used, a shunt resistor based voltage sense pin (rsn) provides current sensing to the controller. 2.3.5. vreg a, vregb for supporting voltages greater than 5.5 v, an internal voltage regulator (vrega, vregb) needs to be used in conjunction with an external npn transistor, a resistor and a capacitor to provide regulated voltage to the ic. 2.3.6. output voltage control the isolated output voltage (vout) is sensed by a resist or divider that provides feedback to the controller through the vsns pin. the voltage error is encoded and transmitted back to the primary side controller across the isolation barrier, which in turn changes the du ty cycle of the transformer driver. the equation for vout is as follows: vout vsns 1 r1 r2 ------- -+ ?? ?? ? r1 + i offset ? =
si88x4x preliminary rev. 0.6 21 2.3.7. compensation the dc-dc converter uses peak current mode control. the loop is compensated by connecting an external resistor in series with a capacitor from the comp pin to gndb . the compensation resistance, rcomp is fixed at 49.9 k ? for si882xx/3xx and 100 k ? for si884xx/6xx to match internal resist ance. capacitance value is given by the following equation, where f c is crossover frequency: for more details on the calculations involved, please see ?an892: design guide for isolated dc/dc using the si882xx/883xx?. 2.3.8. thermal protection a thermal shutdown circuit is included to protect the s ystem from over-temperature events. the thermal shutdown is activated at a junction te mperature that prevents permanent damage from occurring. 2.3.9. cycle skipping cycle skipping is included to reduce switching power losses at light loads. this feature is transparent to the user and is activated automatically at light loads. the product options with integrated power switches (si882xx/3xx) may never experience cycle skipping during operation even at light loads while the external power switch options (si884xx/6xx) are likely to have cycle skipping start at light loads. ccomp 6 2 ?? f c rcomp ?? ?? ---------------------------------------------------------- - =
si88x4x 22 preliminary rev. 0.6 2.3.10. low-voltage configuration the low-voltage configuration is used for converting 3.0 v to 5.5 v. all product options of the si882xx and si883xx are intended for this configuration. an advantage of si88xx devices over other converters that use this same topology is that the output voltage is sensed on the secondary side without requiring addition al optocouplers and support circuitry to bias those optocouplers. this allows the dc-dc to operate with superior line and load regulation while reducing external components and increasi ng lifetime reliability. in a typical digital signal isolation application, the dc-dc powers the si882xx and si883xx vddb as shown in figure 8. in addition to powering the is olated side of the dc-dc can deliver up to 2 w of power to other loads. the dc-dc requires an input capacitor, c2, blocking capacitor, c1, transformer, t1, rectifying diode, d1, and an output capacitor, c3. resistors r1 and r2 divide the output voltage to match the internal reference of the error amplifier. type 1 loop compensation made by rcomp and ccomp are required at the comp pin. though it is not necessary for normal operation, we recommend that a snubber be used to minimize radiated emissions. more details can be found in ?an892: design guid e for isolated dc-dc using the si882xx/883xx?. figure 8. si88xx block diagram: 3 v?5 v input to 3 v?5 v output a1 a2 b1 b2 cmos isolation fwd. digital channels si8832x freq. control and shutdown soft start uvlo power fet dc-dc controller vsw sh_fc ss vdda css rfsw power fet error amp and compensation encoder uvlo vddb vsns comp vreg r 1 used in applications where converter output is > 5.5 v hvreg reference vin vout c 1 t 1 d 1 c 3 hf rx hf tx hf tx hf tx hf rx hf rx r 2 c 2 rcomp ccomp rev. digital channels
si88x4x preliminary rev. 0.6 23 2.3.11. high-voltage configuration the high-voltage configuration is used for converting up to 24 v to 3.3 v or 5.0 v. all product options of the si884xx and si886xx are intended for this configuration. si884xx and si886xx can be used for dc-dc applications that have primary side voltage greater than 5.5 v. the dc- dc converter uses the isolated flyback topology. with this topology, the switch and se nse resistor are external, allowing higher switching voltages. digital isolator supply vdda of the si884xx and si886xx require a supply less than or equal to 5.5 v. if a suitable supply is not ava ilable on the primary side, the vrega voltage reference with external npn transistor can supply vdda . this eliminates the need to design an additional linear regulator circuit. like the si882xx and si883xx, the output voltage is se nsed on the secondary side without requiring additional optocouplers and support circuitry to bias those optocouple rs. this allows the dc-dc to operate with superior line and load regulation. figure 9 shows the block diagram of an si886xx with external components. si886xx is different from the si882xx/883xx as it has externally-controlled switching fr equency and soft start. the dc-dc requires input capacitor c2, transformer t1, swit ch q1, sense resistor r4, rectifying diode d1 and an output capacitor c3. to supply vdda, q2 transistor is biased and filtered by r3 and c1. exte rnal frequency and soft start behavior is set by css and rfsw. resistors r1 and r2 divide the output voltage to match the internal reference of the error amplifier. type 1 loop compensation made by rcomp and ccomp are required at the comp pin. though it is not necessary for normal operation, we recommend to us e a snubber, to minimize high-frequenc y emissions. for further details, see ?an901: design guide for isolated dc-dc using the si884xx/886xx?. figure 9. si88xx block diagram: 24 v input to 5 v output a1 a2 b1 b2 cmos isolation fwd. digital channel rev. digital channel si8862x freq. control and shutdown soft start uvlo dc-dc controller esw fc_sh ss vdda css rfsw error amp and compensation encoder vddb vsns comp r 2 v out t 1 d 1 c 3 hf rx hf tx hf rx hf tx hf tx hf rx r 1 vreg reference vrega rsn gndp fet driver current sensing r 4 r 3 q 1 c 1 q 2 vin c 2 vregb used in applications where converter output is > 5.5 v rcomp ccomp uvlo vreg reference
si88x4x 24 preliminary rev. 0.6 2.4. transformer design table 10 provides a list of transformers and their parametr ic characteristics that have been validated to work with si882xx/3xx products (input voltage of 3 to 5 v) and si 884xx/si886xx products (input voltage of 24 v). it is recommended that users order the transformers from the vendors per the part numbers given below. refer to an892 and an901 for voltage translation applications not listed below. to manufacture transformers from your preferred suppliers that may not be listed below, please specify to supplier the parametric characteristics as specified in the tabl e below for a given input voltage and isolation rating. table 10. transformer specifications transformer supplier ordering part # input voltage turns ratio leakage inductance primary inductance primary resistance isolation rating umec www.umec-usa.com tg-utb02185s 3.0 ? 5.5 v 4.0:1 105 nh max 2 h 5% 0.05 ? max 2.5 kvrms tg-utb02205s 24 v 3.0:1 800 nh max 25 h 5% 0.135 ? max 2.5 kvrms coilcraft www.coilcraft.com ta7608-al 3.0 ? 5.5 v 4.0:1 60 nh max 2 h 10% 0.036 ? max 2.5 kvrms
si88x4x preliminary rev. 0.6 25 3. digital isolator device operation 3.1. device startup outputs are held low during power up until vddx is above the uvlo threshold for time period t su . following this, the outputs follow the states of inputs. 3.2. undervoltage lockout undervoltage lockout (uvlo) is provided to prevent erroneous operation during device startup and shutdown or when vddx is below its specified o perating circuits range. both side a and side b each have their own undervoltage lockout monitors. each side can enter or exit uvlo independently. for example, side a unconditionally enters uvlo when vdda falls below v dduv? and exits uvlo when vdda rises above v dduv+ . side b operates the same as side a with respect to its vdd supply. 3.3. layout recommendations to ensure safety in the end us er application, high voltage circ uits (i.e., circuits with >30 v ac ) must be physically separated from the safety extra-low voltage circuits (selv is a circuit with <30 v ac ) by a certain distance (creepage/clearance). if a component, su ch as a digital isolator, straddles this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating (commonly referred to as working voltage protection ). table 4 and table 6 detail the working voltage and creepage/clearance capabilities of the si88xx. these tables also deta il the component standards (ul1577, vde0884-10, csa 5a), which are readily accepted by certification bodies to provide proof for end-system specifications requirements. refer to the end-system specification (61010-1, 60950-1, 60601-1, etc.) requirements before starting any design that uses a digital isolator. table 11. si88xx logic operation vi input vddi 1,2 , 3 , 4 vddo 1,2 , 3 , 4 vo output comments h p p h normal operation. lp p l xu p p l 4 h 4 upon transition of vddi from unpow- ered to powered, v o returns to the same state as v i . x p up undetermined upon tran sition of vddo from unpowered to powered, v o returns to the same state as v i . notes: 1. vddi and vddo are the input and output power supplies. vi and vo are the re spective input and output terminals. 2. p = powered; up = unpowered. 3. note that an i/o can power the die for a given side through an internal diode if its sour ce has adequate current. this situation should be avoided. we recommend that i/o's not be driven high when primary side supply is turned off or when in dc-dc shutdown mode. 4. see "5. ordering guide" on page 38 for details. this is the selectable fail-safe operating mode (ordering option). when vddb is powered via the primary side and the integrated dc-dc, the default outputs are undetermined as secondary side power is not available when primary side power shuts off.
si88x4x 26 preliminary rev. 0.6 3.3.1. supply bypass the si88xx family requires a 0.1 f bypass capacitor bet ween all vddx and their associated gndx. the capacitor should be placed as close as possible to the package. to enhance the robustness of a design, the user may also include resistors (50?300 ? ) in series with the inputs and outputs if the system is excessively noisy. 3.3.2. output pin termination the nominal output impedance of an isolat or driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series term ination resistor and channel resistance of the output driver fet. when driving high-impedance terminated pcb traces, output pins should be source-ter minated to minimize reflections. 3.4. fail-saf e operating mode si88xx devices feature a selectable (by ordering option ) mode whereby the default ou tput state (when the input supply is unpowered) can either be a logic high or lo gic low when the output supply is powered. see table 11 and table 13 for more information.
si88x4x preliminary rev. 0.6 27 3.5. typical perfor mance characteristics the typical performance charac teristics are for information only. refer to table 2 for s pecification limits. the data below is for all channels switching. figure 10. si88240 typical v dda supply current vs. data rate (5 and 3.3 v operation) figure 12. si88241 typical v dda supply current vs. data rate (5 and 3.3 v operation) figure 14. si88242 typical v dda supply current vs. data rate (5 and 3.3 v operation) figure 11. si88240 typical v ddb supply current vs. data rate (5 and 3.3 v operation) figure 13. si88241 typical v ddb supply current vs. data rate (5 and 3.3 v operation) figure 15. si88242 typical v ddb supply current vs. data rate (5 and 3.3 v operation) 0 5 10 15 20 25 30 02 04 06 08 01 0 0 idda (ma) data rate (mbps) 5v 3.3v 0 5 10 15 20 25 30 0 2 04 06 08 01 0 0 idda (ma) data rate (mbps) 5v 3.3v 0 5 10 15 20 25 30 0 2 04 06 08 01 0 0 idda (ma) data rate (mbps) 5v 3.3v 0 5 10 15 20 25 30 0 20406080100 iddb (ma) data rate (mbps) 5v 3.3v 0 5 10 15 20 25 30 0 20406080100 iddb (ma) data rate (mbps) 5v 3.3v 0 5 10 15 20 25 30 0 20406080100 iddb (ma) data rate (mbps) 5v 3.3v
si88x4x 28 preliminary rev. 0.6 figure 16. si88243 typical v dda supply current vs. data rate (5 and 3.3 v operation) figure 18. si88244 typical v dda supply current vs. data rate (5 and 3.3 v operation) figure 17. si88243 typical v ddb supply current vs. data rate (5 and 3.3 v operation) figure 19. si88244 typical v ddb supply current vs. data rate (5 and 3.3 v operation) 0 5 10 15 20 25 30 0 2 04 06 08 01 0 0 idda (ma) data rate (mbps) 5v 3.3v 0 5 10 15 20 25 30 0 2 04 06 08 01 0 0 idda (ma) data rate (mbps) 5v 3.3v 0 5 10 15 20 25 30 0 20406080100 iddb (ma) data rate (mbps) 5v 3.3v 0 5 10 15 20 25 30 0 20406080100 iddb (ma) data rate (mbps) 5v 3.3v
si88x4x preliminary rev. 0.6 29 figure 20. propagation delay vs. temperature 10.0 11.0 12.0 13.0 14.0 15.0 16.0 17.0 18.0 19.0 20.0 r 40c +25c +125c propagation delay, ns temperature tplh 3.3v tplh 5.0v tphl 3.3v tphl 5.0v
si88x4x 30 preliminary rev. 0.6 figure 21. efficiency vs. load current over temperature (3.3 to 3.3 v) figure 23. efficiency vs. load current over temperature (5.0 to 3.3 v) figure 22. efficiency vs. load current over temperature (3.3 to 5.0 v) figure 24. efficiency vs. load current over temperature (5.0 to 5.0 v) 0 10 20 30 40 50 60 70 80 0 50 100 150 200 250 300 350 400 450 efficiency (%) iload (ma ) 25c 125c r 40c 0 10 20 30 40 50 60 70 80 0 100 200 300 400 500 600 efficiency (%) iload (ma ) 25c 125c r 40c 0 10 20 30 40 50 60 70 80 0 50 100 150 200 250 300 efficiency (%) i load (ma) 25c 125c r 40c 0 10 20 30 40 50 60 70 80 0 100 200 300 400 500 efficiency (%) iload (ma ) 25c 125c r 40c
si88x4x preliminary rev. 0.6 31 figure 25. 5 v?5 v vout startup vs.time (no load) figure 27. 5 v?5 v vout startup vs.time (50 ma load current) figure 26. 5 v?5 v vout startup vs.time (10 ma load current) figure 28. 5 v?5 v vout startup vs.time (400 ma load current) v: ?? 1v/div h: ? 2ms/div v: ?? 1v/div h: ? 2ms/div v: ?? 1v/div h:? 2ms/div v: ?? 1v/div h: ? 2ms/div v: ?? 1v/div h: ? 5ms/div
si88x4x 32 preliminary rev. 0.6 figure 29. 5 v?5 v vout load transient response, 10% to 90% load figure 30. typical i-v curve for vrega/b 3.80 4.00 4.20 4.40 4.60 4.80 5.00 voltage, v current, p a
si88x4x preliminary rev. 0.6 33 4. pin descriptions figure 31. si8824x pin configurations isolation ? barrier 1 2 3 4 5 6 9 10 20 19 18 17 16 15 12 11 hf xmtr hf xmtr hf rcvr hf rcvr gndp vsw vddp vdda gnda sh a3 a4 gndb vddb dnc nc vsns comp b3 b4 7 8 14 13 a1 a2 b1 b2 hf xmtr hf xmtr hf rcvr hf rcvr si88240 isolation ? barrier 20 19 18 17 16 15 12 11 hf xmtr hf xmtr hf rcvr hf rcvr gndp vsw vddp vdda gnda sh a3 a4 gndb vddb dnc nc vsns comp b3 b4 14 13 a1 a2 b1 b2 hf xmtr hf xmtr hf rcvr hf rcvr si88241 isolation ? barrier 1 2 3 4 5 6 9 10 20 19 18 17 16 15 12 11 hf xmtr hf xmtr hf rcvr hf rcvr gndp vsw vddp vdda gnda sh a3 a4 gndb vddb dnc nc vsns comp b3 b4 7 8 14 13 a1 a2 b1 b2 hf xmtr hf xmtr hf rcvr hf rcvr si88242 isolation ? barrier 1 2 3 4 5 6 9 10 20 19 18 17 16 15 12 11 hf xmtr hf xmtr hf rcvr hf rcvr gndp vsw vddp vdda gnda sh a3 a4 gndb vddb dnc nc vsns comp b3 b4 7 8 14 13 a1 a2 b1 b2 hf xmtr hf xmtr hf rcvr hf rcvr si88243 isolation ? barrier 1 2 3 4 5 6 9 10 20 19 18 17 16 15 12 11 hf xmtr hf xmtr hf rcvr hf rcvr gndp vsw vddp vdda gnda sh a3 a4 gndb vddb dnc nc vsns comp b3 b4 7 8 14 13 a1 a2 b1 b2 hf xmtr hf xmtr hf rcvr hf rcvr si88244 1 2 3 4 5 6 9 10 7 8
si88x4x 34 preliminary rev. 0.6 figure 32. si8834x pinout diagrams isolation ? barrier 1 2 3 4 5 6 22 24 23 21 20 19 gndp vsw vddp vdda gnda nc gndb vddb dnc nc vsns comp si88341 7 8 18 17 nc sh_fc ss nc 11 12 14 13 hf xmtr hf xmtr hf rcvr hf rcvr a3 a4 b3 b4 9 10 16 15 a1 a2 b1 b2 hf xmtr hf xmtr hf rcvr hf rcvr isolation ? barrier 1 2 3 4 5 6 22 24 23 21 20 19 gndp vsw vddp vdda gnda nc gndb vddb dnc nc vsns comp si88340 7 8 18 17 nc sh_fc ss nc isolation ? barrier 1 2 3 4 5 6 22 24 23 21 20 19 gndp vsw vddp vdda gnda nc gndb vddb dnc nc vsns comp si88343 7 8 18 17 nc sh_fc ss nc isolation ? barrier 1 2 3 4 5 6 22 24 23 21 20 19 gndp vsw vddp vdda gnda nc gndb vddb dnc nc vsns comp si88342 7 8 18 17 nc sh_fc ss nc 11 12 14 13 hf xmtr hf xmtr hf rcvr hf rcvr a3 a4 b3 b4 9 10 16 15 a1 a2 b1 b2 hf xmtr hf xmtr hf rcvr hf rcvr 11 12 14 13 hf xmtr hf xmtr hf rcvr hf rcvr a3 a4 b3 b4 9 10 16 15 a1 a2 b1 b2 hf xmtr hf xmtr hf rcvr hf rcvr 11 12 14 13 hf xmtr hf xmtr hf rcvr hf rcvr a3 a4 b3 b4 9 10 16 15 a1 a2 b1 b2 hf xmtr hf xmtr hf rcvr hf rcvr isolation ? barrier 1 2 3 4 5 6 22 24 23 21 20 19 gndp vsw vddp vdda gnda nc gndb vddb dnc nc vsns comp si88344 7 8 18 17 nc sh_fc ss nc 11 12 14 13 hf xmtr hf xmtr hf rcvr hf rcvr a3 a4 b3 b4 9 10 16 15 a1 a2 b1 b2 hf xmtr hf xmtr hf rcvr hf rcvr
si88x4x preliminary rev. 0.6 35 figure 33. si8844x pinout diagrams isolation ? barrier 1 2 3 4 5 6 9 10 20 19 18 17 16 15 12 11 hf xmtr hf xmtr hf rcvr hf rcvr gndp rsn esw vdda gnda vrega a3 a4 gndb vddb vregb nc vsns comp b3 b4 7 8 14 13 a1 a2 b1 b2 hf xmtr hf xmtr hf rcvr hf rcvr si88443 isolation ? barrier 10 1 2 3 4 5 6 9 20 19 18 17 16 15 12 11 hf xmtr hf xmtr hf rcvr hf rcvr gndp rsn esw vdda gnda vrega a3 a4 gndb vddb vregb nc vsns comp b3 b4 7 8 14 13 a1 a2 b1 b2 hf xmtr hf xmtr hf rcvr hf rcvr si88442 isolation ? barrier 1 2 3 4 5 6 9 10 20 19 18 17 16 15 12 11 hf xmtr hf xmtr hf rcvr hf rcvr gndp rsn esw vdda gnda vrega a3 a4 gndb vddb vregb nc vsns comp b3 b4 7 8 14 13 a1 a2 b1 b2 hf xmtr hf xmtr hf rcvr hf rcvr si88444 isolation ? barrier 1 2 3 4 5 6 9 10 20 19 18 17 16 15 12 11 hf xmtr hf xmtr hf rcvr hf rcvr gndp rsn esw vdda gnda vrega a3 a4 gndb vddb vregb nc vsns comp b3 b4 7 8 14 13 a1 a2 b1 b2 hf xmtr hf xmtr hf rcvr hf rcvr si88440 isolation ? barrier 1 2 3 4 5 6 9 10 20 19 18 17 16 15 12 11 hf xmtr hf xmtr hf rcvr hf rcvr gndp rsn esw vdda gnda vrega a3 a4 gndb vddb vregb nc vsns comp b3 b4 7 8 14 13 a1 a2 b1 b2 hf xmtr hf xmtr hf rcvr hf rcvr si88441
si88x4x 36 preliminary rev. 0.6 figure 34. si8864x pinout diagrams isolation ? barrier 1 2 3 4 5 6 22 24 23 21 20 19 gndp rsn esw vdda gnda vrega gndb vddb vregb nc vsns comp si88641 7 8 18 17 nc sh_fc ss nc 11 12 14 13 hf xmtr hf xmtr hf rcvr hf rcvr a3 a4 b3 b4 9 10 16 15 a1 a2 b1 b2 hf xmtr hf xmtr hf rcvr hf rcvr isolation ? barrier 1 2 3 4 5 6 22 24 23 21 20 19 gndp rsn esw vdda gnda vrega gndb vddb vregb nc vsns comp si88640 7 8 18 17 nc sh_fc ss nc isolation ? barrier 1 2 3 4 5 6 22 24 23 21 20 19 gndp rsn esw vdda gnda vrega gndb vddb vregb nc vsns comp si88643 7 8 18 17 nc sh_fc ss nc isolation ? barrier 1 2 3 4 5 6 22 24 23 21 20 19 gndp rsn esw vdda gnda vrega gndb vddb vregb nc vsns comp si88642 7 8 18 17 nc sh_fc ss nc 11 12 14 13 hf xmtr hf xmtr hf rcvr hf rcvr a3 a4 b3 b4 9 10 16 15 a1 a2 b1 b2 hf xmtr hf xmtr hf rcvr hf rcvr 11 12 14 13 hf xmtr hf xmtr hf rcvr hf rcvr a3 a4 b3 b4 9 10 16 15 a1 a2 b1 b2 hf xmtr hf xmtr hf rcvr hf rcvr 11 12 14 13 hf xmtr hf xmtr hf rcvr hf rcvr a3 a4 b3 b4 9 10 16 15 a1 a2 b1 b2 hf xmtr hf xmtr hf rcvr hf rcvr isolation ? barrier 1 2 3 4 5 6 22 24 23 21 20 19 gndp rsn esw vdda gnda vrega gndb vddb vregb nc vsns comp si88644 7 8 18 17 nc sh_fc ss nc 11 12 14 13 hf xmtr hf xmtr hf rcvr hf rcvr a3 a4 b3 b4 9 10 16 15 a1 a2 b1 b2 hf xmtr hf xmtr hf rcvr hf rcvr
si88x4x preliminary rev. 0.6 37 table 12. si88x4x pin descriptions pin name description dc-dc input side vddp power stage primary power supply. vrega voltage reference output for external voltage regulator pin. gndp power stage ground. esw power stage external switch driver output. vsw power stage intern al switch output. ss soft startup control. sh, sh_fc shutdown and switch frequency control. rsn power stage current sense input. dc-dc output side vsns power stage feedback input. comp power stage compensation. vregb voltage reference output for external voltage regulator pin. dnc do not connect; leave open. nc no connect; this pin is not connected to the silicon. digital isolator vdda side vdda primary side signal power supply. a1?a4 i/o signal channel 1?4. gnda primary side signal ground. digital isolator vddb side vddb secondary side signal power supply. b1?b4 i/o signal channel 1?4. gndb secondary side signal ground.
si88x4x 38 preliminary rev. 0.6 5. ordering guide table 13. si88x4x ordering guide 1,2,3,4 part # dc-dc shutdown soft start control frequency control external switch forward digital reverse digital package product options available now si88240ed-is y n n n 4 0 wb soic-20 si88241ed-is y n n n 3 1 wb soic-20 si88242ed-is y n n n 2 2 wb soic-20 si88243ed-is y n n n 1 3 wb soic-20 si88244ed-is ynnn 0 4 wb soic-20 contact silicon labs for availability si88240bd-is y n n n 4 0 wb soic-20 si88241bd-is y n n n 3 1 wb soic-20 si88242bd-is y n n n 2 2 wb soic-20 si88243bd-is y n n n 1 3 wb soic-20 si88244bd-is y n n n 0 4 wb soic-20 si88340ed-is y y y n 4 0 wb soic-24 si88341ed-is y y y n 3 1 wb soic-24 si88342ed-is y y y n 2 2 wb soic-24 si88343ed-is y y y n 1 3 wb soic-24 si88344ed-is y y y n 0 4 wb soic-24 si88440ed-is n n n y 4 0 wb soic-20 si88441ed-is n n n y 3 1 wb soic-20 si88442ed-is n n n y 2 2 wb soic-20 si88443ed-is n n n y 1 3 wb soic-20 si88444ed-is n n n y 0 4 wb soic-20 si88640ed-is y y y y 4 0 wb soic-24 si88641ed-is y y y y 3 1 wb soic-24 SI88642ED-IS y y y y 2 2 wb soic-24 si88643ed-is y y y y 1 3 wb soic-24 si88644ed-is y y y y 0 4 wb soic-24 notes: 1. all packages are rohs-compliant with pea k solder reflow temperatures of 26 0 c according to the jedec industry standard classifications. 2. ?si? and ?si? are used interchangeably. 3. aec-q100 qualified. 4. all si88xxxex product options are defaul t output high on input power loss. all si 88xxxbx product options are default low. see "3. digital isolator device operation" on p age 25 for more details about default output behavior.
si88x4x preliminary rev. 0.6 39 6. package outline: 20-pin wide body soic figure 35 illustrates the package details for the 20-pin wide-bod y soic package. table 14 lists the values for the dimensions shown in the illustration. figure 35. 20-pin wide body soic
si88x4x 40 preliminary rev. 0.6 table 14. 20-pin wide body soic package diagram dimensions dimension min max a ? 2.65 a1 0.10 0.30 a2 2.05 ? b0 . 3 10 . 5 1 c0 . 2 00 . 3 3 d 12.80 bsc e 10.30 bsc e1 7.50 bsc e 1.27 bsc l0 . 4 01 . 2 7 h0 . 2 50 . 7 5 0 8 aaa ? 0.10 bbb ? 0.33 ccc ? 0.10 ddd ? 0.25 eee ? 0.10 fff ? 0.20 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jedec outline ms-013, variation ac. 4. recommended reflow profile per jedec j-st d-020c specification for small body, lead-free components.
si88x4x preliminary rev. 0.6 41 7. land pattern: 20-pin soic figure 36 illustrates the pcb land patter n details for the 20-pin soic packag e. table 15 lists the values for the dimensions shown in the illustration. figure 36. 20-pin soic pcb land pattern table 15. 24-pin soic pcb land pattern dimensions dimension mm c1 9.40 e1 . 2 7 x1 0.60 y1 1.90 notes: 1. this land pattern design is based on ipc-7351 design guidelines for density level b (median land protrusion). 2. all feature sizes shown are at maxi mum material condition (mmc), and a card fabrication toleranc e of 0.05 mm is assumed.
si88x4x 42 preliminary rev. 0.6 8. package outline: 24-pin wide body soic figure 37 illustrates the package details for the 24-pin wide-bod y soic package. table 16 lists the values for the dimensions shown in the illustration. figure 37. 24-pin wide body soic
si88x4x preliminary rev. 0.6 43 table 16. 24-pin wide body soic package diagram dimensions dimension min max a ? 2.65 a1 0.10 0.30 a2 2.05 ? b 0.31 0.51 c 0.20 0.33 d 15.40 bsc e 10.30 bsc e1 7.50 bsc e 1.27 bsc l 0.40 1.27 h 0.25 0.75 0 8 aaa ? 0.10 bbb ? 0.33 ccc ? 0.10 ddd ? 0.25 eee ? 0.10 fff ? 0.20 notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jedec outline ms-013, variation ad. 4. recommended reflow profile per jedec j-std-020 specification for small body, lead-free components.
si88x4x 44 preliminary rev. 0.6 9. land pattern: 24-pin soic figure 38 illustrates the pcb land patter n details for the 24-pin soic packag e. table 17 lists the values for the dimensions shown in the illustration. figure 38. 24-pin soic pcb land pattern table 17. 24-pin soic pcb land pattern dimensions dimension mm c1 9.40 e1 . 2 7 x1 0.60 y1 1.90 notes: 1. this land pattern design is based on ipc-7351 design guidelines for density level b (median land protrusion). 2. all feature sizes shown are at maxi mum material condition (mmc), and a card fabrication toleranc e of 0.05 mm is assumed. ?
si88x4x preliminary rev. 0.6 45 10. top markings 10.1. si88x4x top marking (20-pin wide body soic) 10.2. top marking explanatio n (20-pin wide body soic) line 1 marking: base part number ordering options see ordering guide for more information. si88x4 = 5 kv rated 4 channel digital isolator with dc-dc converter x=2, 4 2 = dc-dc shutdown 4 = external fet y = number of reverse channels z=e, b e = default high b = default low r=d d = 5 kvrms isolation rating line 2 marking: yy = year ww = workweek assigned by the assembly house. corresponds to the year and workweek of the mold date. tttttt = mfg code manufacturing code from assembly purchase order form. line 3 marking: circle = 1.5 mm diameter (center justified) ?e4? pb-free symbol country of origin iso code abbreviation tw = taiwan ?
si88x4x 46 preliminary rev. 0.6 10.3. si88x4x top marking (24-pin wide body soic) 10.4. top marking explanatio n (24-pin wide body soic) line 1 marking: base part number ordering options see ordering guide for more information. si88x4 = 5kv rated 4 channel digital isolator with dc-dc converter x=3, 6 3 = full-featured dc-dc with internal fet 6 = full-featured dc-dc with external fet y = number of reverse channels z=e, b e = default high b = default low r=d d = 5 kvrms isolation rating line 2 marking: yy = year ww = workweek assigned by the assembly house. corresponds to the year and workweek of the mold date. tttttt = mfg code manufacturing code from assembly purchase order form. line 3 marking: circle = 1.5 mm diameter (center justified) ?e4? pb-free symbol country of origin iso code abbreviation tw = taiwan
si88x4x preliminary rev. 0.6 47 d ocument c hange l ist revision 0.5 to revision 0.6 ? reformatted figures. ? corrected typos. ? added text for clarity.
si88x4x 48 preliminary rev. 0.6 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. patent notice silicon labs invests in research and development to help our customers differentiate in the market with innovative low-power, s mall size, analog- intensive mixed-signal soluti ons. silicon labs' extensive pat ent portfolio is a testament to our unique approach and world-clas s engineering team. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no responsibili ty for errors and omissions, and disclaim s responsibility for any consequences resulting from the use of information included herein. additionally, silicon laboratorie s assumes no responsibility for the functioning of undescribed fea- tures or parameters. silicon laboratories reserves the right to make changes without further notice. silicon laboratories makes no warran- ty, representation or guarantee regarding t he suitability of its products for any par ticular purpose, nor does silicon laborato ries assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, in cluding without limitation consequential or incidental damages . silicon laboratories products are not designed, intended, or authorized for use in applica tions intend- ed to support or sustain life, or for any other application in which the failure of the silicon laboratories product could crea te a situation where personal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unaut horized application, buyer shall indemnify and hold silicon laboratories harmle ss against all claims and damages.

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